1. Field of the Invention
The present invention relates to programmable integrated circuit structures and methods for fabrication thereof, and more particularly to amorphous silicon antifuses and circuits and routing structures incorporating antifuses, and methods for fabrication thereof.
2. Description of Related Art
Programmable semiconductor devices include programmable read only memories ("PROMs"), programmable logic devices ("PLDs"), and programmable gate arrays. Programmable elements suitable for one or more of these device types include fuses and antifuses.
A fuse is a structure which electrically couples a first terminal to a second terminal, but which, when programmed by passage of sufficient current between its terminals, electrically decouples the first terminal from the second terminal. A fuse typically is of a conductive material which has a geometry that causes portions of the conductive fuse material to physically separate from each other when heated to the extent that an open circuit results.
An antifuse is a structure which when unprogrammed does not electrically couple its first and second terminals, but which, when programmed by applying sufficient voltage between the first and second terminals, permanently electrically connects the first and second terminals. One type of antifuse comprises a highly resistive material between two terminals of conductive material, the antifuse material being such that when sufficient voltage is applied, the resulting current heats the materials and causes portions of the conductive material to extend into the resistive material and form a permanent conductive path. Another type of antifuse comprises an amorphous silicon which forms conductive polysilicon when heated. In PROM devices, for example, the advantages of the antifuse technology over fuse technology include scalability and reduced programming current requirement. Various antifuses are disclosed in U.S. Pat. No. 3,675,090, issued Jul. 4, 1972 to Neale, and U.S. Pat. No. 3,792,319, issued Feb. 12, 1974 to Tsang.
The use of amorphous silicon in the fabrication of semiconductor threshold and switch devices is well known. As more fully discussed in the aforementioned Neale patent, various semiconductor switch devices comprise a "pore" filled with amorphous silicon, which contacts a lower electrode forming surface and an upper electrode forming surface. The electrodes are variously described as comprising a refractory material alone (Neale, FIG. 4), a refractory material connected at its upper surface to an aluminum conductor (Neale, FIG. 6), a refractory material overlaying an aluminum conductor (Neale, FIGS. 8-9), and a refractory material connected at its end to an aluminum conductor (Neale, FIG. 11).
Neale recognized that two important objectives were to obtain switch devices with a very low leakage current in the preprogrammed condition and a fairly consistent programming voltage value. An aspect of the Neale invention was to fabricate the semiconductor switch device so as to present a very small cross-sectional area of semiconductor material for current flow to minimize leakage current paths therethrough. Unfortunately, these measures alone are insufficient to achieve low leakage current along with a low and consistent programming voltage, which is desired in many applications.
Antifuses have been used successfully in programmable interconnect substrates, memories, and some types of PLDs.
An antifuse suitable for use in an electrically programmable interconnection substrate is disclosed in U.S. Pat. No. 4,458,297, issued Jul. 3, 1984 to Stopper et al. A silicon substrate for hybrid circuits is divided into discrete areas for hosting integrated circuit chips and providing the bonding pads for the signal connections between the chips and the substrate. Transverse pad lines and net lines are provided, which are insulated at the crossover points except for respective via holes, each furnished with a pad of amorphous silicon material. The lines are arranged so that a number of pads can be connected to each other as desired by programming. See also Herbert Stopper, "A Wafer with Electrically Programmable Interconnections," in Proceedings of the International Solid State Circuits Conference, Feb. 15, 1985, pp. 263-269.
Antifuses used in interconnect substrates tend to require high programming voltages and currents. As the interconnection substrate does not contain sensitive integrated active semiconductor devices, and as programming is completed prior to attachment and bonding of the functional die, the antifuses between the pad and net lines are designed to minimize the leakage current, and do not minimize the programming current and programming voltage.
Specifically, the device described by Stopper requires that a threshold voltage of 20 volts be exceeded to initiate the switching process into the programmed state. Many devices designed to operate at 5 volts (the typical integrated circuit operating voltage) cannot tolerate voltages as high as 20 volts due to junction breakdown voltages between 12-20 volts. Although higher junction breakdown voltages can be obtained in integrated circuits, thicker insulation layers throughout the circuit, larger transistors, lower doping levels, and other component adjustments must be provided. These changes cause a reduction in the operating frequency as well as an increase in the size of the circuit. Thus a higher breakdown voltage is accompanied by a direct trade-off in circuit performance.
An example of antifuse technology for a bipolar PROM is illustrated in FIGS. 1 and 2, which are taken from Brian Cook and Steve Keller, "Amorphous Silicon Antifuse Technology for Bipolar PROMS," 1986 Bipolar Circuits and Technology Meeting, 1986, pp. 99-100.
In the via antifuse of FIG. 1, first metal comprising aluminum conductor 14 and barrier metal 10 and 11 is provided on an oxide layer 13 overlaying substrate 12. A thick oxide layer 18 is provided over conductor 14 as insulation from second metal. A via etched into oxide layer is lined with a thin film of amorphous silicon 15, which fully overlays and contacts the barrier metal 11 under the via. Second metal comprising barrier metal 16 and aluminum conductor 17 is provided over the via, in contact with the amorphous silicon 15.
The contact antifuse of FIG. 2 is formed over a transistor comprising collector 20, base 21, and emitter 22. Emitter contact is made to a platinum silicide region 23 through a contact hole in oxide 24, which is lined with amorphous silicon film 25. Barrier metal 26 and aluminum conductor 27 overlay the amorphous silicon 25, and are protected by oxide 28.
In the examples of FIGS. 1 and 2, the deposition of the amorphous silicon was a critical step in the process, as the thickness of the film 15 (FIG. 1) and film 25 (FIG. 2) was thought to control the programming voltage. The pre-programmed leakage current was reduced to about 6 microamperes at 2 volts by a high temperature anneal at 450 degrees C. Other factors thought to influence leakage current in the undoped amorphous silicon antifuse were feature size (leakage current proportional) and film thickness (leakage current inversely proportional).
Unfortunately, antifuse technology developed for use in memories is generally too leaky for use in PLDs, as noted by Cook et al. In a PROM, one bit is selected per output at a time; therefore, if the programmable elements are leaky, only one leaky bit loads the sense amplifier. Usually the sense amplifier can tolerate this loading without drastically affecting its functionality or performance. Contrast one type of PLD known as a programmable array logic, which is implemented using PROM technology. The programmable elements are used to configure logic (routing is dedicated and global). In programmable array logic, multiple bits can be accessed and may overload the sense line if the programmable elements are leaky. Overloading the sense line may drastically degrade the performance and in the extreme case, result in functional failure.
Certain techniques have been employed in PLDs using antifuse technology to overcome the problems created by antifuse leakage. One technique uses active semiconductor devices such as diodes or transistors to block the leakage current, an approach which can also be used in memories having leaky antifuses. While this approach is satisfactory in memories and in the logic configuration circuits of PLDs, the technique is not satisfactory for use in the routing circuits of such integrated circuits as the field programmable gate array ("FPGA").
The FPGA, which is distinguished from conventional gate arrays by being user programmable, otherwise resembles a conventional gate array in having an interior matrix of logic blocks and a surrounding ring of I/O interface blocks. Logic functions, I/O functions, and routing of interconnect networks are all user configurable, which affords high density and enormous flexibility suitable for most logic designs. User logic, for example, conventionally is implemented by interconnecting two-input NAND gates into more complex functions. Extensive user configurability of the FPGA is achieved by incorporating a large number of programmable elements into the logic and I/O blocks and the interconnect network. Naturally, the leakage requirement of the programmable elements is stringent, due to the large number of possible connections generally involved and the numerous failure modes that leakage can cause. For instance, leaky programmable elements in the routing areas contribute to high supply current problems, cross talk problems, and performance degradation.
To meet the stringent leakage requirements imposed by FPGAs, conventional fuses and transistor switches generally have been employed. Antifuses using amorphous silicon have not been employed due to their excessive leakage when designed for the programming voltages and currents conventionally used in FPGAs.